1. Field of the Invention
The present invention relates to a timing circuit for synchronization of phase and frequency, and particularly to such a circuit having a highly pipelined structure, thereby optimizing the circuit for use in a high-speed read channel while inducing high latency.
2. Description of the Related Art
A clock and data recovery system, which may be referred to as a channel, invariably requires a timing recovery feedback loop for clock synchronization. Historically, this need has been fulfilled through the use of a phase-locked loop timing circuit. Phase-locked loop timing circuits typically include a frequency integration feedback loop and a phase integration feedback loop. They operate by first ascertaining the timing frequency and timing phase of the target signal, “locking” onto that frequency and phase, and then tracking deviations to both phase and frequency. The process of locking onto the timing frequency and timing phase is generally referred to as the acquisition mode, and the process of tracking deviations is generally referred to as the tracking mode. Phase-locked loop timing circuits are very well known in the literature and are the subject of many patents. For example, see U.S. Pat. Nos. 5,703,539; 5,727,038; 5,745,011; 5,754,607; 5,761,258; 5,793,824; 5,874,863; 5,889,829; 5,986,513; 5,987,085; 6,028,727; 6,066,988; and 6,084,480, the contents of each of which are incorporated herein by reference.
Typically, a frequency integration feedback loop includes a resistor and a capacitor connected in series, with the capacitor also connected to ground; and a phase integration feedback loop includes a voltage-controlled oscillator. The target signal, generally regarded as being an “error” signal because its phase and frequency require adjustment, is provided as input to the frequency integration feedback loop, and the output of that loop is provided as input to the phase integration feedback loop. Hence, the two loops generally operate jointly. However, the joint use of the two feedback loops reduces the stability of the overall circuit, as compared to the stability of each individual feedback loop. The stability of the overall circuit is inversely related to the speed at which the circuit is operated. In other words, if the circuit is operated at a sufficiently low speed, the circuit remains stable, but as the operation speed increases, the circuit tends to become unstable.
If a channel is to operated at a high speed, the feedback loop must be structured in a highly “pipelined” manner; i.e., more feedback elements must be present in the loop. This causes the loop to have a high latency, or time delay, associated with it. A high latency generally causes degraded performance of the timing loop, which in turn requires that the loop bandwidth be reduced in order to maintain loop stability. However, the timing acquisition must be accomplished in as short a time as possible, in order to maintain the speed of the channel and thereby not adversely impact overall system performance. Thus, a dilemma for implementation of high speed channels is presented.